1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device using an SOI (silicon on insulator) substrate.
2. Description of the Related Art
A substrate (an SOI substrate) in which single crystal silicon is provided on an insulating film has been used for high-speed operation and low power consumption of a semiconductor device. A semiconductor device including an N-channel thin film transistor (TFT) and a P-channel TFT has been manufactured with the use of an SOI substrate.
It is generally known that the most suitable orientation of silicon for a TFT varies depending on the structure and use application of the TFT. Single crystal silicon whose plane orientation is (100) is preferably used for a channel of an N-channel TFT while single crystal silicon whose plane orientation is (110) is preferably used for a channel of a P-channel TFT.
In Patent Document 1, an SOI substrate including single crystal silicon whose plane orientation is (100) and single crystal silicon whose plane orientation is (110) is disclosed. Further, a method for manufacturing a semiconductor device in which the single crystal silicon whose plane orientation is (100) is used for a channel of an N-channel TFT and the single crystal silicon whose plane orientation is (110) is used for a channel of a P-channel TFT is disclosed. The manufacturing method will be described below (FIGS. 1A to 1D).
A thermal oxide film 1001 is formed on a surface of a single crystal silicon substrate 1002 whose plane orientation is (110). The thermal oxide film 1001 and a single crystal silicon substrate 1000 whose plane orientation is (100) are bonded to each other. The bonding is performed by annealing at 1100° C. (FIG. 1A). The single crystal silicon substrate 1002 is made thinner by mechanical polishing and chemical etching, thereby forming a single crystal silicon film 1003. A thermal oxide film 1004 is formed on a bottom surface of the single crystal silicon film 1003. The thermal oxide film 1004 and a semiconductor substrate 1005 are bonded to each other (FIG. 1B).
The single crystal silicon substrate 1000 is polished and chemically etched, thereby forming a single crystal silicon film. The single crystal silicon film is formed into an island-like shape so as to form an active layer 1006 of an N-channel TFT 1013. The thermal oxide film 1001 is selectively removed, thereby exposing the single crystal silicon film 1003 which is to be an active layer of a P-channel TFT 1014 (FIG. 1C).
A gate insulating film 1009 is formed over the single crystal silicon film 1003, and a gate insulating film 1010 is formed over the active layer 1006. A gate electrode 1012 is formed over the gate insulating film 1009, and a gate electrode 1011 is formed over the gate insulating film 1010. Doping with N-type impurity ions is performed using the gate electrode 1011 as a mask, thereby forming a source region 1020 and a drain region 1008 of the N-channel TFT. Doping with P-type impurity ions is performed using the gate electrode 1012 as a mask, thereby forming a source region 1021 and a drain region 1007 of the P-channel TFT. Thus, part of the N-channel TFT 1013 in which the single crystal silicon having the (100) plane orientation is used for a channel formation region 1016 and part of the P-channel TFT 1014 in which the single crystal silicon having the (110) orientation is used for a channel formation region 1015 are formed (FIG. 1D). After that, an interlayer insulating film, a contact hole, a source electrode, and a drain electrode are formed.
However, it takes much time to form a single crystal silicon film by making a single crystal silicon substrate thinner by mechanical polishing and chemical etching as disclosed in Patent Document 1; moreover, it is difficult to control the amount of polishing and the amount of etching. As a method for forming a single crystal silicon film from a single crystal silicon substrate, there is a Smart Cut (registered trademark) method in addition to polishing and chemical etching. The Smart Cut method is a method by which a silicon substrate is doped with hydrogen ions so that an embrittlement layer is formed therein and a single crystal silicon film is separated along the embrittlement layer by heat treatment (e.g., Patent Document 2). In the Smart Cut method, by controlling acceleration energy and the dose of hydrogen ions, the thickness of a single crystal silicon film can be controlled.
The above method is applied to the manufacturing method of Patent Document 1 (FIGS. 2A to 2C). A single crystal silicon substrate 1100 whose plane orientation is (100) is doped with hydrogen ions 1105, thereby forming an embrittlement layer 1110. Energy of the hydrogen ions is adjusted so that the embrittlement layer 1110 is formed at a depth of greater than or equal to 50 nm and less than or equal to 200 nm from a surface of the single crystal silicon substrate 1100. Meanwhile, a single crystal silicon substrate 1102 whose plane orientation is (110) is also doped with hydrogen ions 1106 at the same dose as that of the hydrogen ions 1105, thereby forming an embrittlement layer 1111. Energy of the hydrogen ions is adjusted so that the embrittlement layer 1111 is formed at a depth of greater than or equal to 50 nm and less than or equal to 200 nm from a surface of the single crystal silicon substrate 1102 (FIG. 2A).
An oxide film 1101 is formed over the single crystal silicon substrate 1102 by a CVD method, a sputtering method, or the like (FIG. 2B).
Then, the oxide film 1101 and the single crystal silicon substrate 1100 having the (100) orientation are bonded to each other (FIG. 2B). If the bonding is performed by annealing, a single crystal silicon film 1112 and a single crystal silicon film 1113 are separated along the embrittlement layer 1110 and the embrittlement layer 1111, respectively (FIG. 2C). The single crystal silicon film 1112 and the single crystal silicon film 1113 each have a small thickness of greater than or equal to 50 nm and less than or equal to 200 nm; therefore, it is difficult to handle the films.